Exemplary embodiments relate to a nonvolatile memory device and a method of operating the same and, more particularly, to a nonvolatile memory device and a method of operating the same, which are capable of reducing the likelihood of an error when performing a read operation.
In order to increase memory capacity, a higher degree of integration of nonvolatile memory devices may be implemented. From among the nonvolatile memory devices, a NAND flash memory device is advantageous in the higher degree of integration because the NAND flash memory device has a number of memory cells coupled in series together to form one cell string. Accordingly, demand for the NAND flash memory device is increasing.
FIG. 1 is a cross-sectional view showing the cell string structure of a known NAND flash memory device.
Referring to FIG. 1, a string of the NAND flash memory device includes a number of memory cells MC0 to MC31 coupled in series between a source select transistor (not shown) and a drain select transistor (not shown).
Each of the memory cells MC0 to MC31 has a stack type gate in which a gate insulating layer 15, a floating gate 17, a dielectric layer 19, and a control gate 21 are sequentially stacked over a semiconductor substrate 11. Junctions 13 are formed by implanting impurity ions into the semiconductor substrate 11 on both sides of each of the memory cells MC0 to MC31.
The above-described NAND flash memory device is programmed or erased in such a manner that electrons are injected into or emitted from the floating gate 17 in accordance with the Fowler-Nordheim tunneling method in order to control the threshold voltages of the memory cells.
To further increase the memory capacity of the device, a Multi Level Cell (hereinafter referred to as an ‘MLC’), capable of storing data of 2 bits or more in one memory cell, is used. The MLC has two or more data storage states, and the data storage states correspond to respective threshold voltage distributions.
Each of the memory cells MC0 to MC31 is programmed to have a threshold voltage higher than a predefined verification level depending on data to be programmed. The verification level differs depending on the data to be programmed, and it is set lower than a read voltage supplied during a read operation by taking a read margin into consideration. The program threshold voltage of a specific cell, after being programmed, can rise under the influence of subsequent program operations performed on neighboring cells.
Meanwhile, to read data stored in a memory cell selected from among the memory cells MC0 to MC31, a read voltage is supplied to the selected memory cell, and a read pass voltage for forming a channel is supplied to each of the remaining unselected memory cells. Here, if the program threshold voltages of memory cells adjacent to the selected memory cell have excessively risen, an error can occur in the read operation of the selected memory cell.
For example, it is assumed that the selected memory cell (e.g., MC1) has been normally programmed, and the program threshold voltage of at least one of the memory cells MC0 and MC2, adjacent to the selected memory cell MC1, has been excessively increased and is higher than that of the selected memory cell MC1. Here, to perform the read operation, the read voltage is supplied to the selected memory cell MC1, and the read pass voltage is supplied to each of the remaining unselected memory cells MC0 and MC2 to MC31. The read operation is performed by determining the on/off state of the selected memory cell MC1 according to whether a current path is formed in the cell string when the read pass voltage and the read voltage are supplied. Accordingly, for the purpose of a correct read operation, a channel must be formed in the semiconductor substrate 11 (i.e., the semiconductor substrate 11 between the junctions 13), beneath the gate patterns of the unselected memory cells MC0 and MC2 to MC31 that are supplied with the read pass voltage. However, if the program threshold voltage of at least one of the unselected memory cells MC0 and MC2, adjacent to the selected memory cell MC1, has excessively risen and is higher than that of the selected memory cell MC1, the channel may not be formed in at least one of the memory cells MC0 and MC2 adjacent to the selected memory cell MC1. Consequently, when the read operation is performed on the selected memory cell MC1, the selected memory cell MC1 is recognized as an off state irrespective of a level of the read voltage supplied to the selected memory cell MC1, and so the program state of the selected memory cell MC1 is not correctly read. This phenomenon becomes more profound with a reduction in the gap between the memory cells according to the higher degree of integration of the devices.